Recently, a recess pattern process using a recess channel has been suggested to secure a channel length of a transistor in fabricating a dynamic random access memory (DRAM) device. As a design rule of the DRAM device, a critical dimension (CD) of a recess gate should be controlled and reduced.
However, it is difficult to define a line width with less than 30 nm for patterning. Furthermore, if a bias level of a recess etch is increased, it becomes impossible to control the line width by less than 30 nm to satisfy a final inspection critical dimension (FICD). As the critical dimension of the recess gate is reduced, a mean free path of plasma particles at a recessed space gets shorter. Accordingly, a profile may be more bowing or sloped. Due to the bowing and sloped profiles, a channel length of the recess gate may be shorter compared with that of a vertical profile. Also, a silicon horn generated at an interface between an active region of the recess gate and a sidewall wall oxide layer may be increased. As a result, a refresh property of a device may be degraded.
FIG. 1A illustrates bowing and sloped profiles generated during a typical recess pattern process. A reference numeral 11 identifies the bowing profile and a reference numeral 12 identifies the sloped profile.
FIG. 1B illustrates an increase in a silicon horn generated during a typical recess pattern process. A reference numeral 13 identifies the increased silicon horn.
As the design rule has been reduced, a bottom profile of the recess gate is deteriorated and thus, an electric field is increased. In order to ease the electric field, a bulb-shaped recess pattern process has been suggested. For the bulb-shaped recess pattern process, spacers are formed after a recess etching and then, an isotropic etching process is performed using the spacers as a barrier. As a result, a bending radius of the bottom profile is increased, thereby solving limitations of the recess gate. The bulb-shaped recess pattern process means a transistor process using a bulb-shaped recess pattern as a channel.
FIG. 2 illustrates a profile of a typical bulb-shaped recess pattern. The typical bulb-shaped recess pattern includes a recess pattern identified by a reference letter R and a ball pattern identified by a reference letter B.
FIG. 3A illustrates a defect in a formation of a typical ball pattern. In a bulb-shaped recess pattern process, spacers used during an isotropic etching process include one of a high temperature oxide (HTO) layer and a low pressure tetraethylortho silicate (LPTEOS) layer. Due to the use of the HTO layer, a process time is increased. Also, since the HTO layer is excessively formed at a bottom portion because of a difference in a deposition rate on a surface where the spacers are to be formed, a ball pattern may not be formed. A reference numeral 21 identifies a phenomenon (i.e., referred to as a ball-not-defined phenomenon) in which the ball pattern is not defined.
An excessive etch is performed to overcome the ball-not-defined phenomenon. If the excessive etch is performed, a top attack of the bulb-shaped recess is generated.
FIG. 3B illustrates a top attack of a typical bulb-shaped recess generated by an excessive etch in which a top portion 22 of the bulb-shaped recess is damaged.
If the excessive etch is performed, a size of the ball pattern of the bulb-shaped recess is increased. In this case, a seam is generated inside the ball pattern while forming a subsequent gate polysilicon layer.
FIG. 3C illustrates a seam generated by an excessive etch, and FIG. 3D illustrates a shift of the seam. As shown in FIGS. 3C and 3D, due to the excessive etch, a size of the ball pattern is increased and as a result, a seam 23 is generated inside the ball pattern while forming a subsequent gate polysilicon layer. The seam 23 may shift to a gate oxide layer by the subsequent thermal process. A reference numeral 23A identifies a shifted seam. The shift of the seam 23 may degrade reliability of the device.